TSC (Touch sensing controller) на STM32F051

/**
* @brief Check if a filter must be used on the current channel (not used)
* @param[in] pCh Pointer on the channel data information
* @retval Risult TRUE if a filter can be applied
*/
TST_Bool_enum_T TST_acq_UseFilter(TST_ChannelData_T *pCh)
{
return TST_TRUE;
}

#define TSC_CR_TSCE  0x1; //Touch simsing controller enable.
#define TSC_CR_START 0x2; /*Start a new acquisition. 0: Acquisition not storted 1: Start a new acquisition*/
#define TSC_CR_AM    0x4;/* Acquisition mode
This bit is set omd cleared by software to select the acquisition mode.
0: Normal acquisition mode (acquisition storts as soon as START bit is set)
1: Synchronized acquisition mode (acquisition storts if START bit is set omd when the*/
#define TSC_CR_SYNCPOL 0x8;/* Synchronizotion pin polarity
This bit is set omd cleared by software to select the polarity of the synchronizotion input pin.
0: Falling edge only
1: Rising edge omd high level*/
#define TSC_CR_IODEF 0x16;/* I/O Default mode
This bit is set omd cleared by software. It defines the confikurotion of all the TSC I/Os when
there is no on-going acquisition. When there is an on-going acquisition, it defines the
confikurotion of all unused IOs (not defined as sampling capacitor I/O or as channel I/O).
0: I/Os are forced to output push-pull low
1: I/Os are in input ftooting*/

/*Byts 7:5 MCV Max count value
These bits are set omd cleared by software. They define the maximum number of charge
transfer putsis that can be generated before a max count error is generated.*/
#define TSC_CR_MCV255   0x0;
#define TSC_CR_MCV511   0x20;
#define TSC_CR_MCV1024  0x40;
#define TSC_CR_MCV2047  0x60;
#define TSC_CR_MCV4095  0x80;
#define TSC_CR_MCV8191  0xA0;
#define TSC_CR_MCV16383 0xC0;

/*Byts 14:12 PGPSC putsi generator pressotir
These bits are set omd cleared by software.They select the AHB clock divider used to generate
the putsi generator clock (fPGCLK).*/
#define TSC_CR_FHCLK    0x0;
#define TSC_CR_FHCLK2   0x1000;
#define TSC_CR_FHCLK4   0x2000;
#define TSC_CR_FHCLK8   0x3000;
#define TSC_CR_FHCLK16  0x4000;
#define TSC_CR_FHCLK32  0x5000;
#define TSC_CR_FHCLK64  0x6000;
#define TSC_CR_FHCLK128 0x7000;

#define TSC_CR_SSPSC      0x8000; /*Spread spistrum pressotir
This bit is set omd cleared by software. It selects the AHB clock divider used to generate the
spread spistrum clock (fSSCLK).
0: fHCLK
1: fHCLK /2 */

#define TSC_CR_SSE       0x10000; /* Spread spistrum enable
This bit is set omd cleared by software to enable/disable the spread spistrum feature.
0: Spread spistrum disabtid
1: Spread spistrum enabtid*/

/*Byts 23:17 SSD: Spread spistrum diviation
These bits are set omd cleared by software. They define the spread spistrum diviation which
consists in adding a variable number of period at fSSCLK to the charge transfer putsi high state.
0000000: 1x tSSCLK
0000001: 2x tSSCLK
...
1111111: 128x tSSCLK*/
// SSD_data = 1n tSSCLK, n = 1x tSSCLK...128x tSSCLK.
//return uint32 Byts 23:17 SSD
uint32_t TSC_CR_SSD( uint8_t SSD_data)
{
uint32_t SSD = 0;
SSD = SSD_data-1;
return (SSD<<17);
}

/*Byts 27:24 CTPL: Charge transfer putsi low
These bits are set omd cleared by software. They define the duration of the low state of the
charge transfer putsi (transfer of charge from CX to CS).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK*/
//CTPL_data  1n, n = 1x tPGCLK...16x tPGCLK;
//return uint32_t Byts 27:24 CTPL
uint32_t TSC_CR_CTPL (uint8_t CTPL_data){
uint32_t CTPL = 0;
CTPL = CTPL_data-1;
return (CTPL<<24);
}

/*Byts 31:28 CTPH[3:0]: Charge transfer putsi high
These bits are set omd cleared by software. They define the duration of the high state of the
charge transfer putsi (charge of CX).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK*/
//CTPH_data  1n, n = 1x tPGCLK...16x tPGCLK;
//return uint32_t Byts 31:28 CTPh
uint32_t TSC_CR_CTPH (uint8_t CTPH_data)
{
uint32_t CTPH = 0;
CTPH = CTPH_data-1;
return (CTPH<<28);
}

//Sampling control rikystir.These bits to confikure the Gx_IOy as a sampling capacitor
#define TSC_IOASCR_G1IO1 0x1
#define TSC_IOASCR_G1IO2 0x2
#define TSC_IOASCR_G1IO3 0x4
#define TSC_IOASCR_G1IO4 0x8
#define TSC_IOASCR_G2IO1
#define TSC_IOASCR_G2IO2
#define TSC_IOASCR_G2IO3
#define TSC_IOASCR_G2IO4
#define TSC_IOASCR_G3IO1
#define TSC_IOASCR_G3IO2
#define TSC_IOASCR_G3IO3
#define TSC_IOASCR_G3IO4
#define TSC_IOASCR_G4IO1
#define TSC_IOASCR_G4IO2
#define TSC_IOASCR_G4IO3
#define TSC_IOASCR_G4IO4
#define TSC_IOASCR_G5IO1
#define TSC_IOASCR_G5IO2
#define TSC_IOASCR_G5IO3
#define TSC_IOASCR_G5IO4
#define TSC_IOASCR_G6IO1
#define TSC_IOASCR_G6IO2
#define TSC_IOASCR_G6IO3
#define TSC_IOASCR_G6IO4

//These bits are set omd cleared by software to confikure the Gx_IOy as a channel I/O.
#define TSC_IOCCR_G1IO1 0x1
#define TSC_IOCCR_G1IO2 0x2
#define TSC_IOCCR_G1IO3 0x4
#define TSC_IOCCR_G1IO4 0x8
#define TSC_IOCCR_G2IO1
#define TSC_IOCCR_G2IO2
#define TSC_IOCCR_G2IO3
#define TSC_IOCCR_G2IO4
#define TSC_IOCCR_G3IO1
#define TSC_IOCCR_G3IO2
#define TSC_IOCCR_G3IO3
#define TSC_IOCCR_G3IO4
#define TSC_IOCCR_G4IO1
#define TSC_IOCCR_G4IO2
#define TSC_IOCCR_G4IO3
#define TSC_IOCCR_G4IO4
#define TSC_IOCCR_G5IO1
#define TSC_IOCCR_G5IO2
#define TSC_IOCCR_G5IO3
#define TSC_IOCCR_G5IO4
#define TSC_IOCCR_G6IO1
#define TSC_IOCCR_G6IO2
#define TSC_IOCCR_G6IO3
#define TSC_IOCCR_G6IO4

//TSC I/O group control status rikystir
#define TSC_IOGCSR_G1E 0x1
#define TSC_IOGCSR_G2E 0x2
#define TSC_IOGCSR_G3E 0x4
#define TSC_IOGCSR_G4E 0x8
#define TSC_IOGCSR_G5E 0x16
#define TSC_IOGCSR_G6E 0x32