Verilog - небольшая особенность.

module Trs
(input S, R, output Q);
xor xor_01 (G,S,R);
DLC dlc_01 (Q,S,G,R);
endmodule

module MyCF
(input Deactivat,StartTact, Set, ResLim, ResFil, Fillsin, limit,  Run, Zero, Unit, InJamp, InFillsin, InStub1, InFStub, InFStub1, Sel, Sel2,  
 output  Finish, OutJamp, OutFillsin, OutStub1, OutFStub, OutFStub1,  MemoriOut);
wire sig0;
bufif1 bf0(InFillsin, Fillsin, Sel);
Trs trs0(InFillsin, ResFil, trs0_0);
and a0(f1_0, Sel, limit);
Trs trs1(f1_0, ResLim, OutFStub);
not n0(OutFStub1, OutFStub);
xor x0(x0_0, OutFStub1, Sel2);
//bufif1 bf1(InFillsin, InFStub1, InFStub);
bufif1 bf2(OutFillsin, InFillsin, x0_0);
and an0(an0_0,  trs0_0, Unit);
and an1(an1_0,  trs0_0, Zero);
Trs trs2(an0_0, an1_0, trs2_0);
and an2(an2_0,  sig0, trs2_0);
and an3(an3_0,  InJamp, an2_0);
and an4(MemoriOut,  an3_0, StartTact);
and an5(an5_0, Sel, Run);
bufif1 bf3(InJamp, an5_0, an5_0);
bufif1 bf4(Deact, MemoriOut, Deactivat);
Trs trs3(Set, Deact, sig0);
xor x1(x1_0, trs2_0, sig0);
//bufif1 bf4(InJamp, InStub1, InStub1);
and an6(an6_0,  x1_0, x0_0);
not n1(OutStub1, an6_0);
bufif1 bf5(OutJamp, InJamp, an6_0);
and an7(Finish,  MemoriOut, OutFStub);
endmodule

module MyC
(input Deactivat,StartTact, Set, ResLim, ResFil, Fillsin, limit,  Run, Zero, Unit, InJamp, InFillsin, InStub1, InFStub, InFStub1, Sel, Sel2,
 output  Finish, OutJamp, OutFillsin, OutStub1, OutFStub, OutFStub1,  MemoriOut, Se2);
wire sig0;
bufif1 bf0(InFillsin, Fillsin, Sel);
Trs trs0(InFillsin, ResFil, trs0_0);
and a0(f1_0, Sel, limit);
Trs trs1(f1_0, ResLim, OutFStub);
not n0(OutFStub1, OutFStub);
xor x0(x0_0, OutFStub1, Sel2);
bufif1 bf1(InFillsin, InFStub1, InFStub);
bufif1 bf2(OutFillsin, InFillsin, x0_0);
and an0(an0_0,  trs0_0, Unit);
and an1(an1_0,  trs0_0, Zero);
Trs trs2(an0_0, an1_0, trs2_0);
and an2(an2_0,  sig0, trs2_0);
and an3(an3_0,  InJamp, an2_0);
and an4(MemoriOut,  an3_0, StartTact);
and an5(an5_0, Sel, Run);
bufif1 bf3(InJamp, an5_0, an5_0);
bufif1 bf4_(Deact, MemoriOut, Deactivat);
Trs trs3(Set, Deact, sig0);
xor x1(x1_0, trs2_0, sig0);
bufif1 bf4(InJamp, InStub1, InStub1);
and an6(an6_0,  x1_0, x0_0);
not n1(OutStub1, x1_0);
bufif1 bf5(OutJamp, InJamp, an6_0);
and an7(Finish,  MemoriOut, OutFStub);
assign Se2 = Sel;
endmodule

module Smalch (input mset, mreset, output mquit);
Trs Deff_01(mquit,mreset,Out1);
Trs Deff_02(Out1,mreset,Out2);
Trs Deff_03(Out2,,Out3);
not not_01(mquit, Out3);
endmodule

module Smalch1 (input mset, mreset, output mquit, rquit);
Trs Deff_01(mset,mreset,Out1);
Trs Deff_02(Out1,mreset,rquit);
Trs Deff_03(rquit,mreset,mquit);
endmodule

module Lancher (input off, output limit,fillsin,unit);
wire Off_01, Off_02, Off_03, Off_04;
Smalch smch1(,Off_01,limit);
Smalch1 smch2(limit,Off_02,fillsin,Off_01);
Smalch1 smch3(fillsin, off,unit,Off_02);
endmodule

//module MyCount
//(input clk, sens, output ld);
//reg [25:0] count =1;
//reg led_reg = 0;
//assign ld = led_reg;
//wire sens1;
//assign sens1 = sens; 
//always @ (posedge clk)

//begin
//if (sens1 == 1) begin
//led_reg = 0;
// count = count +1;
//if (count == 50000000) begin
//count <= 1;
//led_reg = 1;
//end
//end
//end
//endmodule

module Mych(input clk, output wire led0,led1, led2,led3,led4,led5);
wire  [0:0]se[0:6];
wire  [0:0]se2[0:6];
wire [0:0]ActivMemo[0:5];
wire Start0,Start, Start1,  Set, Fillsin1, EndFillsin, StartTact1;
wire Finish, FinishTact, Unit,InJamp, StartTact,Deactivation;
wire sens, led;
wire limit0;
genvar i;
generate
wire [0:2]OtJam, OutFillsi[0:5], OutStu1[0:5], OutFStu[0:5], OutFStu1[0:5], ORi[0:5], Fini[0:5];
MyCF mycf(Deactivation,StartTact, Set,  ResLim, ResFil, Fillsin1, limit0, Run, Zero, Unit,InJamp,,,,
,Fillsin1,se2[0],Fini[0],ORi[0], OutFillsi[0], OutStu1[0], OutFStu[0], OutFStu1[0], ActivMemo[0]);
bufif1 bf0(FinishTact, ActivMemo[0], ActivMemo[0]);
bufif1 bf1(Finish, Fini[0], Fini[0]);
for (i=0; i<5; i=i+1 ) begin:MyC_generation
//assign se2[i]=se[i];
MyC myc(Deactivation,StartTact, Set,  ResLim, ResFil, Fillsin, limit0, Run, Zero, Unit, ORi[i], OutFillsi[i], OutStu1[i], OutFStu[i], OutFStu1[i]
,se[i],se2[i+1], Fini[i+1],ORi[i+1], OutFillsi[i+1], OutStu1[i+1], OutFStu[i+1], OutFStu1[i+1], ActivMemo[i+1], se2[i]);
bufif1 bf0(FinishTact, ActivMemo[i+1], ActivMemo[i+1]);
bufif1 bf1(Finish, Fini[i+1], Fini[i+1]);
end
endgenerate

Lancher Lanch_01();

assign led0 = ActivMemo [0];
assign led1 = ActivMemo [1];
assign led2 = ActivMemo [2];
assign led3 = ActivMemo [3];
assign led4 = ActivMemo [4];
assign led5 = ActivMemo [5]; 
endmodule