module Trs
(input S, R, 
 output Q);
not n2(R1,R);
and a1(G,S,R1);

module Trs
(input S, R, output Q);//reg
reg Q;
always @(R, S)
  begin
     if(R)
        Q  <= 1'b0;
     else if(S) 
        Q  <= 1'b1;
  end
endmodule

module Trs
(input S, R, output Q);
xor xor_01 (G,S,Q);
DLC dlc_01 (Q,S,G,R);
endmodule

module Cascad
(input StartTact,  InJamp, trsCommand, TrsStep, output MemoriOut);
and an2(an2_0,  trsCommand, TrsStep);
and an3(an3_0,  InJamp, an2_0);
and an4(MemoriOut,  an3_0, StartTact);
endmodule


module MyCF
(input Deactivat,StartTact, Set, ResLim, ResFil, Fillsin, limit,  Run, Zero, Unit, InJampM, InFillsin, InStub1, InFStub, InFStub1,

module Trs
(input S, R, 
 output Q);//reg

module Mych
(input StartTact, Set,  ResLim, ResFil, Fillsin, limit, Run, Zero, Unit, InJamp,
output  FinishTact, Finish, input wire  [1:0]se[0:5], [1:0] se2 [0:4], output wire [1:0]ActivMemo[0:5]);
genvar i;
generate
wire [0:2]OtJam, OutFillsi[0:5], OutStu1[0:5], OutFStu[0:5], OutFStu1[0:5], ORi[0:5], Fini[0:5];