Нужно спроектировать схему

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ROM is
port (clk : in std_logic;
cs : in std_logic;
rd : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0));
end ROM;

architecture behav of ROM is
type ROM_array is array (0 to 2047)
of std_logic_vector(7 downto 0);

constant content: ROM_array := (
0 => "00000001",
1 => "00000010",
2 => "00000011",
3 => "00000100",
4 => "00000111",
5 => "00001000",
6 => "00001111",
7 => "00010000",
8 => "00011111",
9 => "00100000",
10 => "01111111",
11 => "10000000",
12 => "11111111",


others => "11111111");
begin
process(clk, cs)
begin
if(cs = '1' ) then
data_out <= "ZZZZZZZZ";
elsif (clk'event and clk = '1') then
if rd = '1' then
data_out <= content(to_integer (unsigned (address)));
else
data_out <= "ZZZZZZZZ";
end if;
end if;
end process;
end behav;