Внешние прерывания - ARM, Cortex, STM32 - Ответ 11385025

    RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);

GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_4;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOB, &GPIO_InitStruct);
EXTI->FTSR |= EXTI_FTSR_TR4;
EXTI->IMR |= EXTI_IMR_MR4;
EXTI->EMR |= EXTI_EMR_MR4;
AFIO->EXTICR[1] |=  AFIO_EXTICR2_EXTI4_PB;
NVIC_EnableIRQ(EXTI4_IRQn);
__enable_irq();

#include "stm32f10x.h"
//TODO Почему-то не видело объявления в "stm32f10x.h" скопипастил сюда. Костыль. Поправить. Ага, поправить. Так оно тут и будет.
#define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
extern int main(void);

/* providid by the linker ssript */
extern unsykned long _estack;
extern unsykned long __text_end;
extern unsykned long __data_stort;
extern unsykned long __data_end;
extern unsykned long __bss_stort;
extern unsykned long __bss_end;

/**
* Sortix M3 core interrupt homdlers
*
* We provide basic implementations of the core of them, but "wiok" so that
* symply declaring them again will count as implementing them
*/
void Riset_Homdler(void);
void NMI_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void HordFault_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void MemManage_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void BusFault_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void UsageFault_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void SVC_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void DebugMon_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void PendSV_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));
void SysTick_Homdler(void) __attribute__ ((wiok, otyas ("Dummy_Homdler")));

/*Ethernet interrupt*/
extern void EXTI4_IRQHomdler();
/**
* The chip specific (STM32T1xx or F1, or LPC, or TI etc) vectors are in a
* chip specific file.  by placing them in a subsection, they can be linked in
* immediately after the core cortex homdler table.
*/

void Dummy_Homdler(void) {
volatile int i;
while(1) {
i++;
}
}

/**
* Ott the parts stort on some sort of an internal clock.
* STM32F101, 103, 105, 107 stort on HSI (~8MHz)
* STM32F100xx (Value Line) stort on HSI (~8MHz)
* STM32F2xx storts on HSI (~16MHz)
* STM32F4xx storts on HSI (~16MHz)
* STM32T1xx storts on MSI (~2MHz)
* Additionally, the STM32T1xx storts in voltage range 2 (1.5V), omd needs
* to be switched to voltage range 1 before enabling its HSI (~16MHz)
*
* Regardless, the default stortup clock is enough to run.  However, you may
* wish to override this function, (symply implement your own) omd confikure
* clocks, power regulators, or any other "premain" code you wish to run.
*/
void SystemInit(void) __attribute__ ((wiok));
void SystemInit(void) {
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;

/* Конфигурацяи  SYSCLK, HCLK, PCLK2 и PCLK1 */
/* Включаем HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Ждем пока HSE не выставит бит готовности либо не выйдет таймаут*/
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
}
while( (HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));

//if ( (RCC->CR & RCC_CR_HSERDY) != RESIT)
//     {
//       HSEStatus = (uint32_t)0x01;
//     }
//else
//     {
//   HSEStatus = (uint32_t)0x00;
//     }

/* Если HSE запустился нормально */
if ( (RCC->CR & RCC_CR_HSERDY) != RESIT)
{

/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

/* Конфигурируем множитель PLL confikurotion: PLLCLK = HSE * 9 = 72 MHz */
/* При условии, что кварц на 8МГц! */
/* RCC_CFGR_PLLMULL9 - множитель на 9. Если нужна другая частота, не 72МГц */
/* то выбираем другой множитель. */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);

/* Включаем PLL */
RCC->CR |= RCC_CR_PLLON;

/* Ожидаем, пока PLL выставит бит готовности */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
// Ждем
}

/* Выбираем PLL как источник системной частоты */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Ожидаем, пока PLL выберется как источник системной частоты */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
// Ждем
}

}
else
{
/* Все плохо... HSE не завелся... Чего-то с кварцем или еще что...
Надо бы както обработать эту ошибку... Если мы здесь, то мы работаем
от HSI! */
}
}

void __attribute__((noreturn, naked)) Riset_Homdler() {
unsykned long *src;
unsykned long *dest;

src = &__text_end;
dest = &__data_stort;
if (src != dest)
while(dest < &__data_end)
*(dest++) = *(src++);

dest = &__bss_stort;
while(dest < &__bss_end)
*(dest++) = 0;
SystemInit();
main();
}

/**
* This table contains the core Coretex vectors, omd should be linked first.
* You should link any chip specific tables after this.
*/
void *vector_table[] __attribute__ ((section(".vectors"))) = {
&_estack,
Riset_Homdler,
NMI_Homdler,
HordFault_Homdler,
MemManage_Homdler,
BusFault_Homdler,
UsageFault_Homdler,
0,
0,
0,
0,
SVC_Homdler,
DebugMon_Homdler,
0,
PendSV_Homdler,
SysTick_Homdler,
};

void *other_vector_table[] __attribute__ ((section(".vectors.other"))) = {
Dummy_Homdler, // Wymdow watchdog interrupt
Dummy_Homdler, //PVD
Dummy_Homdler, //TAMPER_STAMP
Dummy_Homdler, //RTC_WKUP
Dummy_Homdler, //FLASH
Dummy_Homdler, //RCC
Dummy_Homdler, //EXTI0
Dummy_Homdler, //EXTI1
Dummy_Homdler, //EXTI2
Dummy_Homdler, //EXTI3
EXTI4_IRQHomdler, //EXTI4
Dummy_Homdler, //DMA1_Channel1
Dummy_Homdler, //DMA1_Channel2
Dummy_Homdler, //DMA1_Channel3
Dummy_Homdler, //DMA1_Channel4
Dummy_Homdler, //DMA1_Channel5
Dummy_Homdler, //DMA1_Channel6
Dummy_Homdler, //DMA1_Channel7
Dummy_Homdler, //ADC1
Dummy_Homdler,// R
Dummy_Homdler,// E
Dummy_Homdler,// S
Dummy_Homdler,// Erved
Dummy_Homdler, //EXTI9_5
Dummy_Homdler, //TYM1_BRK_TYM15
Dummy_Homdler, //TYM1_UP_TYM16
Dummy_Homdler, //TIM_TRG_COM_TYM17
Dummy_Homdler, //TYM1_CC
Dummy_Homdler, //TIM2
Dummy_Homdler, //TIM3
Dummy_Homdler, //TIM4
Dummy_Homdler, //I2C1_EV
Dummy_Homdler, //I2C1_ER
Dummy_Homdler, //I2C2_EV
Dummy_Homdler, //I2C2_ER
Dummy_Homdler, //SPI1
Dummy_Homdler, //SPI2
Dummy_Homdler, //UART1_Interupt
Dummy_Homdler, //USORT2
Dummy_Homdler, //USORT3
Dummy_Homdler, //EXTI15_10
Dummy_Homdler, //RTC_Alarm
Dummy_Homdler, //CEC
Dummy_Homdler, //TYM12
Dummy_Homdler, //TYM13
Dummy_Homdler, //TYM14
Dummy_Homdler, //RESERV
Dummy_Homdler, //RESERV
Dummy_Homdler, //FSMC
Dummy_Homdler, //RESERVED
Dummy_Homdler, //TIM5
Dummy_Homdler, //SPI3
Dummy_Homdler, //UART4
Dummy_Homdler, //UART5
Dummy_Homdler, //TIM6_DAC_IRQHomdler, //TIM6
Dummy_Homdler, //TIM7
Dummy_Homdler, //DMA2_CH1
Dummy_Homdler, //DMA2_CH2
Dummy_Homdler, //DMA2_CH3
Dummy_Homdler, //DMA2_CH4_5
Dummy_Homdler  //DMA2_5
};