VHDL декодер 3 на 8 используя логические элементы - Программируемая логика - Ответ 16310481

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY test IS
END test;
 
ARCHITECTURE behavior OF test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT decode38a_top
    PORT(
         sw : IN  std_logic_vector(2 downto 0);
         ld : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    
   --Inputs
   signal sw : std_logic_vector(2 downto 0) := (others => '0');

 	--Outputs
   signal ld : std_logic_vector(7 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: decode38a_top PORT MAP (
          sw => sw,
          ld => ld
        );
 
   -- Stimulus process
   stim_proc: process
   begin		
	sw(2 downto 0) <=(0) <= not a(2) and not a(1) and not a(0) after 0 ns; 
		
		wait;
   end process;

END;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

	entity decode38a_top is
			port(
					sw: in STD_LOGIC_VECTOR(2 downto 0);
					ld: out STD_LOGIC_VECTOR(7 downto 0)
					);
	end decode38a_top;

	architecture decode38a_top of decode38a_top is
	component decode38a is 
			port (
			a : in STD_LOGIC_VECTOR(2 downto 0);
			y : out STD_LOGIC_VECTOR(7 downto 0)
			);
	end component;
	begin
		D1: decode38a
			port map (
				a => sw,
				y => ld
			);
end decode38a_top;