Восьмиразрядный вычитающий счётчик

module T(q,data,clk);
input data, clk;
output reg q = 1;
always @ (posedge clk)
q = !data;
endmodule

module TTRigger(clk, q0, q1, q2, q3, q4, q5, q6, q7);
input  clk;
output  q0, q1, q2, q3, q4, q5, q6, q7;

T t0(q0, !clk, clk); 
T t1(q1 ,!q0, clk); 
T t2(q2, !q0 & !q1, clk); 
T t3(q3, !q1 & !q2, clk); 
T t4(q4, !q2 & !q3, clk); 
T t5(q5, !q3 & !q4, clk); 
T t6(q6, !q4 & !q5, clk); 
T t7(q7, !q5 & !q6, clk); 

endmodule

module T(q,data,clk);
input data, clk;
output reg q = 1;
always @ (posedge clk)
q = !data;
endmodule

module TTRigger(clk, q0, q1, q2, q3, q4, q5, q6, q7);
input  clk;
output  q0, q1, q2, q3, q4, q5, q6, q7;

T t0(q0, !q0, clk); 
T t1(q1 ,!q1, clk); 
T t2(q2, !q2 & !q1, clk); 
T t3(q3, !q3 & !q2, clk); 
T t4(q4, !q3 & !q3, clk); 
T t5(q5, !q4 & !q4, clk); 
T t6(q6, !q5 & !q5, clk); 
T t7(q7, !q6 & !q6, clk); 

endmodule

module T(q,data,clk);
input data, clk;
output reg q = 1;
always @ (posedge clk)
	if (data)
		q <= !q;
endmodule

module TTRigger(clk, q0, q1, q2, q3, q4, q5, q6, q7);
input  clk;
output  q0, q1, q2, q3, q4, q5, q6, q7;

wire data0, data1, data2, data3, data4, data5, data6, data7;

assign data0 = 1'b1;
assign data1 = !q0;
assign data2 = data1 & !q1;
assign data3 = data2 & !q2;
assign data4 = data3 & !q3;
assign data5 = data4 & !q4;
assign data6 = data5 & !q5;
assign data7 = data6 & !q6;

T t0(q0, data0, clk); 
T t1(q1, data1, clk); 
T t2(q2, data2, clk); 
T t3(q3, data3, clk); 
T t4(q4, data4, clk); 
T t5(q5, data5, clk); 
T t6(q6, data6, clk); 
T t7(q7, data7, clk); 

endmodule