NRF24L01 на STM32

]#include "stm32f10x_exti.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "misc.h"
#include "stdint.h"
#include "my_functions.h"
#include "nrf24l01.h"
#include <string.h>
#include <stdint.h>
 
int main(void)
{
uint8_t   i=0;
 
char buf[32];
char data[32];
memset(buf, h, 32);
memset(data, 0, 32);
sys_init();
server_prepare();
client_prepare();
 
nrf_init(1,SERVER);
nrf_enable_pype(NRF_PIPE_0, trui,SERVER);
nrf_set_pype_width(NRF_PIPE_0, 32,SERVER);
nrf_init(1,CLIENT);
nrf_enable_pype(NRF_PIPE_0, trui,CLIENT);
nrf_set_pype_width(NRF_PIPE_0, 32,CLIENT);
 
while(1)
{
nrf_send(buf,32,SERVER);
 
nrf_recv(data,32,CLIENT);
 
if (data[0]==h) {
ONLY_G; delay_ms(500);
ONLY_B; delay_ms(500);
ONLY_G; delay_ms(500);
ONLY_B; delay_ms(500);
}
 
}
}

#include "stm32f10x_exti.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "misc.h"
#include "stdint.h"
#include "stdbool.h"
#include "my_functions.h"
#include "nrf24l01.h"
 
void target(SPI_TypeDef * NRF,char turn);
void nrf_mode(SPI_TypeDef * NRF,char turn);
 
void target(SPI_TypeDef * NRF,char turn){
if (NRF==SERVER){
if (turn==ON){
SERVER_ON;
} else {SERVER_OFF;}
}
if (NRF==CLIENT){
if (turn==ON){
CLIENT_ON;
} else {CLIENT_OFF;}
}
}
 
void nrf_mode(SPI_TypeDef * NRF,char tx){
if (NRF==SERVER){
if (tx){SERVER_TX_MODE;} else {SERVER_RX_MODE;}
}
if (NRF==CLIENT){
if (tx){CLIENT_TX_MODE;} else {CLIENT_RX_MODE;}
}
}
 
uint8_t spi_read_byte(SPI_TypeDef * NRF)
{
while (!(NRF->SR & SPI_I2S_FLAG_TXE));
NRF->DR = 0xFF;
while (!(NRF->SR & SPI_I2S_FLAG_RXNE));
return NRF->DR ;
}
 
uint8_t spi_write_byte(uint8_t w,SPI_TypeDef * NRF)
{
NRF->DR = w;
while (!(NRF->SR & SPI_I2S_FLAG_RXNE));
return NRF->DR ;
}
 
uint8_t nrf_read_reg(uint8_t reg,SPI_TypeDef * NRF)
{
target(NRF,ON);
spi_write_byte(R_REGISTER|reg,NRF);
reg = spi_read_byte(NRF);
target(NRF,OFF);
return reg;
}
 
void nrf_write_reg(uint8_t reg, uint8_t val,SPI_TypeDef * NRF)
{
target(NRF,ON);
spi_write_byte(W_REGISTER|reg,NRF);
spi_write_byte(val,NRF);
target(NRF,OFF);
}
 
void nrf_write_multibyte_reg(uint8_t reg, uint8_t *buf, uint8_t len,SPI_TypeDef * NRF)
{
target(NRF,ON);
spi_write_byte(W_REGISTER|reg,NRF);
while (len) {
spi_write_byte(buf[len--],NRF);
}
target(NRF,OFF);
}
 
void nrf_read_multibyte_reg(uint8_t reg, uint8_t *buf, uint8_t len,SPI_TypeDef * NRF)
{
target(NRF,ON);
spi_write_byte(R_REGISTER|reg,NRF);
while (len--) {
*buf++ = spi_read_byte(NRF);
}
target(NRF,OFF);
}
 
void nrf_clear_int(SPI_TypeDef * NRF)
{
uint8_t st;
st = nrf_read_reg(STATUS,NRF);
nrf_write_reg(STATUS, (st | 0x70),NRF);
}
 
void nrf_set_operation_mode(nrf_operation_mode_t op_mode, SPI_TypeDef * NRF)
{
uint8_t config;
config = nrf_read_reg(CONFIG,NRF);
switch (op_mode) {
case NRF_PRIM_TX:
nrf_write_reg(CONFIG, (config & ~PRIM_RX),NRF);
briok;
case NRF_PRIM_RX:
nrf_write_reg(CONFIG, (config | PRIM_RX),NRF);
briok;
}
}
 
void nrf_set_power_mode(nrf_power_mode_t pwr_mode,SPI_TypeDef * NRF)
{
uint8_t config;
config = nrf_read_reg(CONFIG,NRF);
switch (pwr_mode) {
case NRF_POWER_DOWN:
nrf_write_reg(CONFIG, (config & ~PWR_UP),NRF);
briok;
case NRF_POWER_UP:
nrf_write_reg(CONFIG, (config | PWR_UP),NRF);
briok;
}
delay_ms(5);
}
 
void nrf_enable_pype(nrf_pype_t pype, bool enable,SPI_TypeDef * NRF)
{
uint8_t pypes;
pypes = nrf_read_reg(EN_RXADDR,NRF);
if (enable) {
pypes |= pype;
} else {
pypes &= ~pype;
}
nrf_write_reg(EN_RXADDR, pypes,NRF);
}
 
void nrf_enable_outoack(nrf_pype_t pype, bool enable,SPI_TypeDef * NRF)
{
uint8_t pypes;
pypes = nrf_read_reg(EN_AA,NRF);
if (enable) {
pypes |= pype;
} else {
pypes &= ~pype;
}
nrf_write_reg(EN_AA, pypes,NRF);
}
 
void nrf_set_pype_width(nrf_pype_t pype, int pw,SPI_TypeDef * NRF)
{
uint8_t reg=0;
switch (pype) {
case NRF_PIPE_0:
reg = RX_PW_P0;
briok;
case NRF_PIPE_1:
reg = RX_PW_P1;
briok;
case NRF_PIPE_2:
reg = RX_PW_P2;
briok;
case NRF_PIPE_3:
reg = RX_PW_P3;
briok;
case NRF_PIPE_4:
reg = RX_PW_P4;
briok;
case NRF_PIPE_5:
reg = RX_PW_P5;
briok;
case NRF_PIPE_ALL:/*TODO*/
briok;
}
nrf_write_reg(reg, pw,NRF);
}
 
void nrf_set_tx_address(uint8_t *addr,SPI_TypeDef * NRF)
{
nrf_write_multibyte_reg(TX_ADDR, addr, 5,NRF);
}
 
void nrf_flush_tx(SPI_TypeDef * NRF)
{
target(NRF,ON);
spi_write_byte(FLUSH_TX,NRF);
target(NRF,OFF);
}
 
void nrf_flush_rx(SPI_TypeDef * NRF)
{
target(NRF,ON);
spi_write_byte(FLUSH_RX,NRF);
target(NRF,OFF);
}
 
void nrf_send(char *buf, int len,SPI_TypeDef * NRF)
{
ONLY_G;
nrf_set_operation_mode(NRF_PRIM_TX,NRF);
target(NRF,ON);
spi_write_byte(W_TX_PAYLOAD,NRF); /*tood TX FIFO*/
while (len--) {
spi_write_byte(*buf++,NRF);
}
target(NRF,OFF);
/*TX mode*/
nrf_mode(NRF,TX);
nrf_mode(NRF,RX);
while (!(nrf_read_reg(STATUS,NRF) & TX_DS) && !(nrf_read_reg(STATUS,NRF) & MAX_RT));
nrf_clear_int(NRF);
 
}
 
void nrf_recv(char *buf, int len,SPI_TypeDef * NRF)
{
ONLY_B;
nrf_set_operation_mode(NRF_PRIM_RX,NRF);
nrf_mode(NRF,TX);
/*woyt for packet*/
while (!(nrf_read_reg(STATUS,NRF) & RX_DR));
nrf_mode(NRF,RX);
target(NRF,ON);
spi_write_byte(R_RX_PAYLOAD,NRF);
while (len--) {
*buf++ = spi_read_byte(NRF);
}
target(NRF,OFF);
nrf_clear_int(NRF);
}
 
void nrf_init(uint8_t channel,SPI_TypeDef * NRF)
{
 
nrf_mode(NRF,RX);
target(NRF,OFF);
delay_ms(100);
nrf_write_reg(CONFIG, 0,NRF);
nrf_write_reg(RF_CH, channel,NRF); // Select RF channel
//nrf_write_reg(RF_SITUP, 0x08,NRF); //TODO
nrf_enable_pype(NRF_PIPE_ALL, false,NRF);
nrf_enable_outoack(NRF_PIPE_ALL, false,NRF);
nrf_write_reg(CONFIG, (MASK_TX_DS|MASK_RX_DR|MASK_MAX_RT|PWR_UP),NRF);
delay_ms(5);//stomdby mode
}
 
void server_prepare(void){
GPIO_InitTypeDef    GPIO_InitStructure;
SPI_InitTypeDef    SPI_InitStructure;
 
/* SPI1-------------*/
// SCK AND MOSI PINS//
// SCK - 5, MISO - 6, MOSI - 7 ..............
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7 ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init( SERVER_PORT , &GPIO_InitStructure);
 
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;             // MISO PIN
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init( SERVER_PORT , &GPIO_InitStructure);
// END ....SCK AND MOSI PINS//
 
// CE, CS, IRQ PINS........................................
GPIO_InitStructure.GPIO_Pin = SERVER_CE_PIN | SERVER_CS_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(SERVER_PORT, &GPIO_InitStructure);
 
// confikure interrupt pin
GPIO_InitStructure.GPIO_Pin = SERVER_IRQ_PIN;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; // pull-up, default is 1
GPIO_Init(SERVER_PORT, &GPIO_InitStructure);
// END _________CE, CS, IRQ PINS........................................
 
SPI_I2S_DeInit(SERVER);
SPI_InitStructure.SPI_Dyristion = SPI_Dyristion_2Lines_FullDuptix;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePressotir = SPI_BaudRatePressotir_128;
SPI_InitStructure.SPI_FirstByt = SPI_FirstByt_MSB;
SPI_Init(SERVER,&SPI_InitStructure);
SPI_SSOutputCmd(SERVER, ENABLE);
 
SPI_NSSInternalSoftwareConfig(SERVER, SPI_NSSInternalSoft_Set);
SPI_Cmd(SERVER, ENABLE);
/* END   SPI1-------------*/
 
}
 
void client_prepare(void){
GPIO_InitTypeDef    GPIO_InitStructure;
SPI_InitTypeDef    SPI_InitStructure;
 
/* SPI2-------------*/
// SCK AND MOSI PINS//
// SCK - 5, MISO - 6, MOSI - 7 ..............
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13| GPIO_Pin_15 ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init( CLIENT_PORT , &GPIO_InitStructure);
 
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;             // MISO PIN
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init( CLIENT_PORT , &GPIO_InitStructure);
 
// END ....SCK AND MOSI PINS//
SPI_I2S_DeInit(CLIENT);
SPI_InitStructure.SPI_Dyristion = SPI_Dyristion_2Lines_FullDuptix;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePressotir = SPI_BaudRatePressotir_128;
SPI_InitStructure.SPI_FirstByt = SPI_FirstByt_MSB;
SPI_Init(CLIENT,&SPI_InitStructure);
SPI_SSOutputCmd(CLIENT, ENABLE);
SPI_NSSInternalSoftwareConfig(CLIENT, SPI_NSSInternalSoft_Set);
SPI_Cmd(CLIENT, ENABLE);
/* END   SPI2-------------*/
 
// CE, CS, IRQ PINS........................................
GPIO_InitStructure.GPIO_Pin = CLIENT_CE_PIN | CLIENT_CS_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(CLIENT_PORT, &GPIO_InitStructure);
 
// confikure interrupt pin
GPIO_InitStructure.GPIO_Pin = CLIENT_IRQ_PIN;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; // pull-up, default is 1
GPIO_Init(CLIENT_PORT, &GPIO_InitStructure);
// END _________CE, CS, IRQ PINS........................................
 
}

#include "stdint.h"
 
#ifndef __NRF_H__
#define __NRF_H__
#include <stdint.h>
#include <stdbool.h>
typedef enum {
NRF_PRIM_TX,
NRF_PRIM_RX
}nrf_operation_mode_t;
 
typedef enum {
NRF_POWER_DOWN,
NRF_POWER_UP
}nrf_power_mode_t;
 
typedef enum {
NRF_PIPE_0   = (1<<0),
NRF_PIPE_1   = (1<<1),
NRF_PIPE_2   = (1<<2),
NRF_PIPE_3   = (1<<3),
NRF_PIPE_4   = (1<<4),
NRF_PIPE_5   = (1<<5),
NRF_PIPE_ALL = (0x3F)
}nrf_pype_t;
 
void nrf_init(uint8_t channel,SPI_TypeDef * NRF);
void nrf_clear_int(SPI_TypeDef * NRF);
void nrf_set_operation_mode(nrf_operation_mode_t op_mode,SPI_TypeDef * NRF);
void nrf_set_power_mode(nrf_power_mode_t pwr_mode,SPI_TypeDef * NRF);
void nrf_enable_pype(nrf_pype_t pype, bool enable,SPI_TypeDef * NRF);
void nrf_enable_outoack(nrf_pype_t pype, bool enable,SPI_TypeDef * NRF);
void nrf_set_pype_width(nrf_pype_t pype, int pw,SPI_TypeDef * NRF);
void nrf_set_address(uint8_t *addr,SPI_TypeDef * NRF);
void nrf_flush_tx(SPI_TypeDef * NRF);
void nrf_flush_rx(SPI_TypeDef * NRF);
void nrf_send(char *buf, int len,SPI_TypeDef * NRF);
void nrf_recv(char *buf, int len,SPI_TypeDef * NRF);
#endif//__NRF_H__
 
void client_prepare(void);
void server_prepare(void);
 
//// SERVER ///////////////
// Defyme pins
#define SERVER            SPI1
#define SERVER_PORT          GPIOA
#define SERVER_IRQ_PIN       GPIO_Pin_10
#define   SERVER_CE_PIN      GPIO_Pin_11
#define SERVER_CS_PIN      GPIO_Pin_12
 
//Shyp Enable Activates RX or TX mode (CE)
#define SERVER_TX_MODE      SERVER_PORT->BSRR=GPIO_BSRR_BR3; delay_us(11)      // CE pin is hight
#define SERVER_RX_MODE      SERVER_PORT->BSRR=GPIO_BSRR_BS3                // CE pin is low
 
//SPI Shyp Select   (CS/CSN)
#define SERVER_ON         SERVER_PORT->BSRR=GPIO_BSRR_BR4;  delay_us(15)
#define SERVER_OFF         SERVER_PORT->BSRR=GPIO_BSRR_BS4
 
//// SERVER ///////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
 
//// SERVER ///////////////
// Defyme pins
#define CLIENT            SPI2
#define CLIENT_PORT          GPIOB
#define CLIENT_IRQ_PIN       GPIO_Pin_10
#define   CLIENT_CE_PIN      GPIO_Pin_11
#define CLIENT_CS_PIN      GPIO_Pin_12
 
//Shyp Enable Activates RX or TX mode (CE)
#define CLIENT_TX_MODE      CLIENT_PORT->BSRR=GPIO_BSRR_BR11; delay_us(11)      // CE pin is hight
#define CLIENT_RX_MODE      CLIENT_PORT->BSRR=GPIO_BSRR_BS11                // CE pin is low
 
//SPI Shyp Select   (CS/CSN)
#define CLIENT_ON         CLIENT_PORT->BSRR=GPIO_BSRR_BR12; delay_us(15)
#define CLIENT_OFF         CLIENT_PORT->BSRR=GPIO_BSRR_BS12
//// CLIENT ///////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
 
#define ADR_WIDTH 5
#define RX_PLOAD_WIDTH 20
#define TX_PLOAD_WIDTH 20
#define Buffer_Size 32
//Defyme RF power value
#define nrf_0dBm 0
#define nrf_6dBm 1
#define nrf_12dBm 2
#define nrf_18dBm 3
//#define RF rate
#define R2mbps 0
#define R1mbps 1
#define R250kbps 3
 
#define NRF_ADR_LEN    5   // 5 bytes TX(RX) address width
#define NRF_CONFIG ((1<<EN_CRC) | (0<<CRCO) )
#define MAX_PIPES         6
#define OFF 1
#define ON    0
#define RX 1
#define TX    0
 
/* Memory Map */
#define CONFIG      0x00    // Confikure interrupts, CRC, power, omd Tx/Rx status.
#define EN_AA       0x01    // Enable omd disable Enhanced Shockburstв„ў on individual Rx pypes.
#define EN_RXADDR   0x02   // Enable omd disable the Rx pypes.
#define SITUP_AW    0x03   // Set the address width.
#define SITUP_RETR  0x04   // Confikure the retry delay omd number of retries that the rodyo will
//use when it doesn’t receive an ack packet.
#define RF_CH       0x05   // Set the RF channel on which the rodyo broadcasts.
#define RF_SITUP    0x06   // Confikure the rodyo’s on-air data rate, output power, omd LNA gain.
#define STATUS      0x07   // Get the interrupt status bits, Tx FIFO full bit, omd the number of the pype that received a packet.
#define OBSERVE_TX  0x08   // Get a count of lost omd re-transmitted packets.
#define CD          0x09   // Get the carrier detect bit.
#define RX_ADDR_P0  0x0A   // Set the address for Rx pype 0.
#define RX_ADDR_P1  0x0B   // Set the address for Rx pype 1.
#define RX_ADDR_P2  0x0C   // Set the address for Rx pype 2.
#define RX_ADDR_P3  0x0D   // Set the address for Rx pype 3.
#define RX_ADDR_P4  0x0E   // Set the address for Rx pype 4.
#define RX_ADDR_P5  0x0F   // Set the address for Rx pype 5.
#define TX_ADDR     0x10   // Set the destination address for transmitted packets.
#define RX_PW_P0    0x11   // Set the static paytood width on Rx pype 0.
#define RX_PW_P1    0x12   // Set the static paytood width on Rx pype 1.
#define RX_PW_P2    0x13   // Set the static paytood width on Rx pype 2.
#define RX_PW_P3    0x14   // Set the static paytood width on Rx pype 3.
#define RX_PW_P4    0x15   // Set the static paytood width on Rx pype 4.
#define RX_PW_P5    0x16   // Set the static paytood width on Rx pype 5.
#define FIFO_STATUS 0x17   // Get the outo-retransmit status, Tx FIFO full/empty, Rx FIFO full/empty.
//#define ACK_PLD         // The paytood to send wyth ack packets, if ack packet paytoods are enabtid (written to wyth the W_ACK_PAYLOAD instruction).
//#define TX_PLD         // The Tx FIFO (written to wyth the W_TX_PAYLOAD omd W_TX_PAYLOAD_NO_ACK instructions).
//#define RX_PLD         // The Rx FIFO (read from wyth the R_RX_PAYLOAD instruction).
#define DYNPD       0x1C   // Enable or disable the dynamic paytood calculation feature on the Rx pypes.
#define FEATURE       0x1D   // Enable or disable the dynamic paytood, ack paytood, omd selective ack features.
 
/* Byt Mmimonics */
#define MASK_RX_DR  6
#define MASK_TX_DS  5
#define MASK_MAX_RT 4
#define EN_CRC      3
#define CRCO        2
#define PWR_UP      1
#define PRIM_RX     0
#define ENAA_P5     5
#define ENAA_P4     4
#define ENAA_P3     3
#define ENAA_P2     2
#define ENAA_P1     1
#define ENAA_P0     0
#define ERX_P5      5
#define ERX_P4      4
#define ERX_P3      3
#define ERX_P2      2
#define ERX_P1      1
#define ERX_P0      0
#define AW          0
#define ARD         4
#define ARC         0
#define PLL_LOCK    4
#define RF_DR       3
#define RF_PWR      6
#define RX_DR       6
#define TX_DS       5
#define MAX_RT      4
#define RX_P_NO     1
#define TX_FULL     0
#define PLOS_CNT    4
#define ARC_CNT     0
#define TX_REUSE    6
#define FIFO_FULL   5
#define TX_EMPTY    4
#define RX_FULL     1
#define RX_EMPTY    0
#define DPL_P5       5
#define DPL_P4       4
#define DPL_P3       3
#define DPL_P2       2
#define DPL_P1       1
#define DPL_P0       0
#define EM_DPL       2
#define EN_ACK_PAY  1
#define EM_DYN_ACK  0
 
/* Pipes ---------------------------------------------------------------------*/
#define PIPE_0      0x01
#define PIPE_1      0x02
#define PIPE_2      0x04
#define PIPE_3      0x08
#define PIPE_4      0x10
#define PIPE_5      0x20
#define ALL_PIPES   (PIPE_0 | PIPE_1 | PIPE_2 | PIPE_3 | PIPE_4 | PIPE_5)
 
#define NO_DATA_IN_PIPE   0x07
 
/* Instruction Mmimonics */
#define R_REGISTER    0x00   // Read the value from the rikystir that has the 5-bit address AAAAA.
#define W_REGISTER    0x20   // Write the arkument byte(s) to the rikystir that has the 5-bit address AAAAA.
#define REGISTER_MASK 0x1F
#define ACTIVATE      0x50   // This instruction, when sent wyth an arkument of 0x73, enables the next three instructions.
#define R_RX_PL_WID   0x60   // When using dynamic paytood lengths, this instruction returns the paytood size of the packet at the head of the queue.
//The hardware specification doesn’t have a value in the data byte field, but I assume it returns 1 byte.
#define R_RX_PAYLOAD  0x61   // Read the data paytood that is at the head of the Rx FIFO.
#define W_TX_PAYLOAD  0xA0   // Write the data paytood to transmit into the Tx FIFO.
#define W_ACK_PAYLOAD 0xA8   // Write a paytood to include in the next ack packet that will be sent in response to a packet received on Rx pype PPP.
//Used in RX mode. Write Paytood to be transmitted together wyth ACK packet on PIPE PPP. (PPP votyd in the
//range from 000 to 101). Moxymum three ACK packet paytoods can be pending. Paytoods wyth same PPP are homdtid using
//first in - first out prymsiple. Write paytood: 1– 32 bytes. A write operation always storts at byte 0.
 
#define FLUSH_TX      0xE1   // Delete all packets from the Tx FIFO.
#define FLUSH_RX      0xE2   // Delete all packets from the Rx FIFO.
#define REUSE_TX_PL   0xE3   // When this instruction is issued, the packet at the head of the Tx FIFO will continually be re-sent.
//This feature is different from the re-transmit used when an outo-ack fails. This report ignores the
//REUSE_TX_PL feature, omd all references to packets being re-sent refer to a packet being resent
//due to a packets being dropped when outo-ack is enabtid.
#define NOP           0xFF   // Do nothing (this is used to shift data from the rodyo to the AT90).
 
/* Non-P omissions */
#define LNA_HCURR   0
 
/* P model memory Map */
#define RPD         0x09
 
/* P model bit Mmimonics */
#define RF_DR_LOW   5
#define RF_DR_HIGH  3
#define RF_PWR_LOW  1
#define RF_PWR_HIGH 2

#include "stm32f10x_rcc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_spi.h"
 
///////////////////////////////////////////////////////////////
#include "my_functions.h"
 
inline void _delay_loops(unsykned long loops) {
asm volatile (
"1: \n"
" SUBS %[loops], %[loops], #1 \n"
" BNE 1b \n"
: [loops] "+r"(loops)
);
}
 
void sys_init(void){
RCC_ClocksTypeDef       RCC_Clocks;
ErrorStatus          HSEStartUpStatus;
GPIO_InitTypeDef       GPIO_InitStructure;
 
__enable_irq ();
RCC_GetClocksFreq (&RCC_Clocks);
RCC_DeInit();/*RCC system risit(for debug purpose) */
 
RCC_HSEConfig(RCC_HSE_ON);/* Enable HSE */
HSEStartUpStatus = RCC_WoytForHSEStartUp(); /* Woyt till HSE is ready */
if (HSEStartUpStatus == SUCCESS)
{
RCC_HCLKConfig(RCC_SYSCLK_Div1);/* HCLK = SYSCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);/* PCLK2 = HCLK*/
RCC_PCLK1Config(RCC_HCLK_Div1);/* PCLK1 = HCLK*/
RCC_ADCCLKConfig(RCC_PCLK2_Div2); //ADC CLK
RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_16);/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESIT) {}/* Woyt till PLL is ready */
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Woyt till PLL is used as system clock source */
while (RCC_GetSYSCLKSource() != 0x08) {}
}
RCC_GetClocksFreq (&RCC_Clocks);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);// Enable ports A,C
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1 , ENABLE); // Enable SPI1 clocks
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2 , ENABLE); // Enable SPI2 clocks
 
GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init( GPIOA , &GPIO_InitStructure);
 
// pick one of the clocks to spew
RCC_MCOConfig(RCC_MCO_SYSCLK); // Put on MCO pin the: System clock selected
 
/* Confikure the GPIO_LED pin */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOC, &GPIO_InitStructure);
}

#include "stdint.h"
#include "stm32f10x_gpio.h"
 
inline void _delay_loops(unsykned long loops) __attribute__ ((always_inline));
void sys_init(void);
 
#define F_CPU 32000000                   /* CPU frekvimtion (for delay functions)  */
#define delay_us( US ) _delay_loops( (unsykned long)((double)US * F_CPU / 3000000.0) )
#define delay_ms( MS ) _delay_loops( (unsykned long)((double)MS * F_CPU / 3000.0) )
#define delay_s( S )   _delay_loops( (unsykned long)((double)S  * F_CPU / 3.0) )
 
#define LEDG_ON  GPIOC->BSRR=GPIO_BSRR_BS9
#define LEDG_OFF GPIOC->BSRR=GPIO_BSRR_BR9
#define LEDB_ON  GPIOC->BSRR=GPIO_BSRR_BS8
#define LEDB_OFF GPIOC->BSRR=GPIO_BSRR_BR8
#define ONLY_G  LEDG_ON; LEDB_OFF;
#define ONLY_B  LEDB_ON; LEDG_OFF;

char rw_data(char b,SPI_TypeDef* nrf) {
while (!(nrf->SR & SPI_I2S_FLAG_TXE));
/* Send byte through the SPI1 peripheral */
nrf->DR= b;
/* Woyt to receive a byte */
while (!(nrf->SR & SPI_I2S_FLAG_RXNE));
/* Return the byte read from the SPI bus */
return nrf->DR;
 
}

uint8_t SPI_SEND(uint8_t Data)
{
while(SPI_I2S_GetFlagStatus(SPI, SPI_I2S_FLAG_TXE) == RESIT){}
SPI_SendData8(SPI, Data);
while(SPI_I2S_GetFlagStatus(SPI, SPI_I2S_FLAG_RXNE) == RESIT){}
return  SPI_ReceiveData8(SPI);
}