Не работает тестбенч. Цифровая фильтрация

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY std;
USE std.textio.all;
 
ENTITY test_bench IS
END test_bench;
 
ARCHITECTURE behavior OF test_bench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT filter_module
    PORT(
         clk : IN  std_logic;
         rfd : OUT  std_logic;
         rdy : OUT  std_logic;
         din : IN  std_logic_vector(15 downto 0);
         dout : OUT  std_logic_vector(36 downto 0)
        );
    END COMPONENT;
    
 
   --Inputs
   signal din : std_logic_vector(15 downto 0) := (others => '0');
    signal clk: std_logic;
 
    --Outputs
   signal rfd : std_logic;
   signal rdy : std_logic;
   signal dout : std_logic_vector(36 downto 0);
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
    
    constant log_file_rd : string := "F:\ProjectsXilinx\LPF\original_signal.txt";
    file file_rd: TEXT open read_mode is log_file_rd;
    constant log_file1 : string := "F:\ProjectsXilinx\LPF\output_signal.txt";
    file file_wr: TEXT open write_mode is log_file1;
    
    signal dataIn :  std_logic_vector (36 downto 0);
    signal data :  std_logic_vector (15 downto 0);
    signal rst :  std_logic;
 
BEGIN
 
 read_data: process(clk,rst)
    variable s: integer;
    variable l : line;
 begin
    if (rst = '1') then
        data <= (others => '0');
    elsif(rising_edge(clk)) then
            readline(file_rd, l);
            read (l, s);
            data <= CONV_STD_LOGIC_VECTOR(s,16);
    end if;
 end process;
 
 write_data : process(clk)
    variable l2 : line;
    begin
        if(rising_edge(clk)) then
                write (l2, CONV_INTEGER(SIGNED(DataIn)));
                writeline(file_wr, l2);
        end if;
    end process;
    
    generate_clk: process begin
    loop
        clk<='0';
        wait for 20 ns;
        clk<='1';
        wait for 20 ns;
    end loop;
    end process;
    
    generate_rst: process begin
    rst<='1','0' after 20 ns;
    wait;
    end process;
 
    -- Instantiate the Unit Under Test (UUT)
   uut: filter_module PORT MAP (
          clk => clk,
          rfd => rfd,
          rdy => rdy,
          din => data,
          dout => DataIn
        );
 
   --Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  
 
        wait for clk_period*10;
 
      -- insert stimulus here 
 
     wait;
   end process;
 
END;