SystemVerilog. case(1'b1) vs priority casez (1'b1)

module priEncode
(
    input logic r0,r1,r2,
	 output logic [2:0] gnt
);

logic [2:0] req;

assign req ={r2,r1,r0}; 

always_comb begin

gnt = 0;

priority casez (1'b1)
//case(1'b1)
    req[0] : gnt[0] = 1;
	 req[1] : gnt[1] = 1;
	 req[2] : gnt[2] = 1;
endcase

end

endmodule: priEncode

    logic r0,r1,r2;
	 logic [2:0] gnt;

	 priEncode priEncode(.r0(r0),.r1(r1),.r2(r2),.gnt(gnt));
	 
	 initial begin
	 gnt=3'b000;
	    $monitor($time, 
      " r0=%b r1=%b r2=%b gnt=%b",
      r0,r1,r2,gnt);
		
		#10 r0 = 1'b1; r2 = 1'b1; r1 = 1'b1;
		//$display(" r0=%b r1=%b r2=%b gnt=%b",
      //r0,r1,r2,gnt);

      #10 r0 = 1'b1; r1 = 1'b0; r2 = 1'b0;
//		$display(" r0=%b r1=%b r2=%b gnt=%b",
//      r0,r1,r2,gnt);
		#10 r0 = 1'b0; r1 = 1'b1; r2 = 1'b0;
//		$display(" r0=%b r1=%b r2=%b gnt=%b",
//      r0,r1,r2,gnt);
		#10 r0 = 1'b1; r1 = 1'b0; r2 = 1'b0;
//		$display(" r0=%b r1=%b r2=%b gnt=%b",
//      r0,r1,r2,gnt);
		#10 r0 = 1'b1; r1 = 1'b1; r2 = 1'b1;
//		$display(" r0=%b r1=%b r2=%b gnt=%b",
//      r0,r1,r2,gnt);
	
		#10 $finish;
		end