Базовые вещи при освоении ПЛИС в части ввода-вывода информации

module RStrigger(input R,S, output Q,iQ);
wire or1o,or2o;
nor or1(or1o,or2o,R);
nor or2(or2o,or1o,S);
assign Q = or1o;
assign iQ = or2o;
endmodule

`timescale 1ns / 1ns 
module RStrigger_tb; 
wire Q_out; 
wire iQ_out;
reg t_R, t_S; 
RStrigger example(.R(t_R), .S(t_S), .Q(Q_out), .iQ(iQ_out)); 
initial 
begin 
t_R = 1'b0; t_S = 1'b0; #5;
t_R = 1'b1; t_S = 1'b0; #5;
t_R = 1'b0; t_S = 1'b1; #5;
t_R = 1'b1; t_S = 1'b1; #5;
end 
endmodule

module shift4bit(clock, data, out, outRegA, outRegB, outRegC);
input clock;
input [3:0] data;
output [3:0] out;
output [3:0] outRegA;
output [3:0] outRegB;
output [3:0] outRegC;
reg [3:0] RegA;
reg [3:0] RegB;
reg [3:0] RegC;
 
always @(posedge clock) begin
RegA <= data;
RegB <= RegA;
RegC <= RegB;
end
 
assign out = data;
assign outRegA = RegA;
assign outRegB = RegB;
assign outRegC = RegC;
 
endmodule

`timescale 1ns / 1ps
module shift4bit_tb; 
// Inputs
reg [3:0] data;
reg clock;
// Outputs
wire [3:0] out;
wire [3:0] outRegA;
wire [3:0] outRegB;
wire [3:0] outRegC;
// Instantiate the Unit Under Test (UUT)
shift4bit uut (.clock(clock),.data(data),.out(out),.outRegA(outRegA),.outRegB(outRegB),.outRegC(outRegC));
initial begin
// Initialize Inputs
data  = 4'd0;
clock  = 1'b1;
// Wait 100 ns for global reset to finish
#20;
// Add stimulus here
data = 4'd1; #20;
data = 4'd2; #20;
data = 4'd3; #20;
data = 4'd4; #20;
data = 4'd5; #20;
data = 4'd6; #20;
data = 4'd7; #20;
data = 4'd8; #20;
end
always #10 clock = ~clock;  
endmodule

(input S, R, 
 output reg Q);
always @(*) begin
Q =0;
if (S==1) Q=1;
if (R==1) Q=0;
end
endmodule

module randnum (signal, clock, r, c_out, pos_neg_edge, signal_for_rattling, mask_for_signal, signal_with_rattling, signal_after_filtering_from_bouncing);
input signal;
input clock;
reg [3:0] n;
reg c;
reg [$clog2(DEBOUNCE_LIMIT)-1:0] r_Count = 0;
reg r_State = 1'b0;
 
output [3:0] r;
output c_out;
output pos_neg_edge;
output signal_for_rattling;
output mask_for_signal;
output signal_with_rattling;
output signal_after_filtering_from_bouncing;
//Parameters
parameter DELAY = 10;
parameter DEBOUNCE_LIMIT = 20;
reg [DELAY-1:0] signal_delay;
//
always @(posedge clock) begin
    n <= $random%15;
    signal_delay <= {signal_delay[DELAY-2:0], signal};
    if (signal_with_rattling !== r_State && r_Count < DEBOUNCE_LIMIT-1) begin
    r_Count <= r_Count + 1;
    end
    else if (r_Count == DEBOUNCE_LIMIT-1) 
    begin
    r_State <= signal_with_rattling;
    r_Count <= 0;
    end
    else 
    begin
    r_Count <= 0;
    end
end
assign r = n;
assign c_out = ($signed(n) < $signed(4'b0000)) ? 1'b1 : 1'b0;
assign pos_neg_edge = (signal != signal_delay[DELAY-1]) ? 1'b1 : 1'b0;
assign signal_for_rattling = signal || pos_neg_edge; 
assign mask_for_signal = !(c_out && pos_neg_edge);
assign signal_with_rattling = signal_for_rattling && mask_for_signal;
assign signal_after_filtering_from_bouncing = r_State;
endmodule

`timescale 1ns / 1ps
module randnum_tb; 
// Inputs
reg clock;
reg signal;
// Outputs
wire [3:0] r;
wire c_out;
wire pos_neg_edge;
wire signal_for_rattling;
wire mask_for_signal;
wire signal_with_rattling;
wire signal_after_filtering_from_bouncing;
// Instantiate the Unit Under Test (UUT)
randnum uut (.signal(signal),.clock(clock),.r(r),.c_out(c_out),.pos_neg_edge(pos_neg_edge),.signal_for_rattling(signal_for_rattling),.mask_for_signal(mask_for_signal),.signal_with_rattling(signal_with_rattling),.signal_after_filtering_from_bouncing(signal_after_filtering_from_bouncing));
initial begin
// Initialize Inputs
clock  = 1'b1;
#10;
signal = 1'b0; #100;
signal = 1'b1; #100;
signal = 1'b0; #100;
// Wait 100 ns for global reset to finish
end
always #0.5 clock = ~clock;  
endmodule