Тест энкодера и декодера на Verilog для FPGA

`timescale 1ns / 1ps
 
// ==========================================================
// ТЕСТБЕНЧ (TOP MODULE)
// ==========================================================
module testbench();
    reg clk;
    reg reset;
    reg [7:0] data_in;
    reg k_in;
 
    wire [9:0] encoded_10b;
    wire disp_enc;
    
    wire [7:0] data_out;
    wire k_out;
    wire coding_err;
    wire disp_dec;
    wire disp_err;
 
    // 1. Екземпляр Енкодера
    encoder_8b10b enc (
        .reset(reset),
        .SBYTECLK(clk),
        .K(k_in),
        .ebi(data_in),
        .tbi(encoded_10b),
        .disparity(disp_enc)
    );
 
    // 2. Екземпляр Декодера (підключений до виходу енкодера)
    decoder_8b10b dec (
        .reset(reset),
        .RBYTECLK(clk),
        .tbi(encoded_10b),
        .K_out(k_out),
        .ebi(data_out),
        .coding_err(coding_err),
        .disparity(disp_dec),
        .disparity_err(disp_err)
    );
 
    // Генерация тактового сигнала (50 МГц)
    always #10 clk = ~clk;
 
    initial begin
        // Ініціалізація
        clk = 0;
        reset = 1;
        data_in = 8'h00;
        k_in = 0;
 
        $display("\n==========================================================================");
        $display(" DATA IN | K |  10B CODE  | DATA OUT | K_OUT | ERR | RESULT");
        $display("==========================================================================");
 
        #25 reset = 0;
 
        // Тестовые данные
        send_byte(8'hBC, 1); // K28.5 (Comma)
        send_byte(8'h45, 0); 
        send_byte(8'h00, 0);
        send_byte(8'hFF, 0);
        send_byte(8'h01, 0);
        send_byte(8'h02, 0);
        send_byte(8'h03, 0);
        send_byte(8'h04, 0);
        send_byte(8'h05, 0);
        send_byte(8'h55, 0);
        send_byte(8'h07, 0);
        send_byte(8'h08, 0);
        send_byte(8'h09, 0);
        send_byte(8'h10, 0);
        send_byte(8'h08, 0);
        send_byte(8'h09, 0);
        send_byte(8'h10, 0);
        repeat(2) @(posedge clk);
        #100 $finish;
    end
 
    // Таск 
    task send_byte(input [7:0] b, input k);
        begin
            data_in = b;
            k_in = k;
            @(posedge clk);
            #5; 
            $display("  0x%h   | %b | %b |   0x%h   |   %b   |  %b  | %s", 
                data_in, k_in, encoded_10b, data_out, k_out, coding_err,
                (data_in == data_out && k_in == k_out) ? "SUCCESS" : "FAIL");
        end
    endtask
 
endmodule
 
// ==========================================================
// МОДУЛЬ ЭНКОДЕРА  
// ==========================================================
module encoder_8b10b (
    input reset,
    input SBYTECLK,
    input K,
    input [7:0] ebi,
    output [9:0] tbi,
    output reg disparity
);
    wire L40, L04, L13, L31, L22, AeqB, CeqD;
    wire PD_1S6, NDOS6, PDOS6, ND_1S6;
    wire ND_1S4, PD_1S4, NDOS4, PDOS4;
    wire DISPARITY6;
    reg COMPLS6, COMPLS4;
    wire NAO, NBO, NCO, NDO, NEO, NIO;
    wire NFO, NGO, NHO, NJO;
    wire A,B,C,D,E,F,G,H;      
    assign {H,G,F,E,D,C,B,A} = ebi[7:0];
    reg a,b,c,d,e,i,f,g,h,j;  
    assign tbi[9:0] = {a,b,c,d,e,i,f,g,h,j};
 
    always @(posedge SBYTECLK, posedge reset)
        if (reset) begin
            disparity <= 1'b0; {a,b,c,d,e,i,f,g,h,j} <= 10'b0; 
        end else begin
            disparity <= (PDOS4 | NDOS4) ^ DISPARITY6;
            {a,b,c,d,e,i,f,g,h,j} <= { NAO^COMPLS6, NBO^COMPLS6, NCO^COMPLS6, 
                                     NDO^COMPLS6, NEO^COMPLS6, NIO^COMPLS6,
                                     NFO^COMPLS4, NGO^COMPLS4, 
                                     NHO^COMPLS4, NJO^COMPLS4 };    
        end
 
    assign AeqB = (A & B) | (!A & !B);
    assign CeqD = (C & D) | (!C & !D);
    assign L40 = A & B & C & D;
    assign L04 = !A & !B & !C & !D;
    assign L13 = (!AeqB & !C & !D) | (!CeqD & !A & !B);
    assign L31 = (!AeqB & C & D) | (!CeqD & A & B);
    assign L22 = (A & B & !C & !D) | (C & D & !A & !B) | (!AeqB & !CeqD);
    assign PD_1S6 = (E & D & !C & !B & !A) | (!E & !L22 & !L31);
    assign NDOS6 = PD_1S6;
    assign PDOS6 = K | (E & !L22 & !L13);
    assign ND_1S6 = K | (E & !L22 & !L13) | (!E & !D & C & B & A);
    assign ND_1S4 = F & G;
    assign NDOS4 = (!F & !G);
    assign PD_1S4 = (!F & !G) | (K & ((F & !G) | (!F & G)));
    assign PDOS4 = F & G & H;
    assign DISPARITY6 = disparity ^ (NDOS6 | PDOS6);
 
    always @(posedge SBYTECLK, posedge reset)
        if(reset) begin COMPLS4 <= 0; COMPLS6 <= 0; end
        else begin
            COMPLS4 <= (PD_1S4 & !DISPARITY6) | (ND_1S4 & DISPARITY6);
            COMPLS6 <= (PD_1S6 & !disparity) | (ND_1S6 & disparity);
        end
 
    reg tNAO, tNBOx, tNBOy, tNCOx, tNCOy, tNDO, tNEOx, tNEOy, tNIOw, tNIOx, tNIOy, tNIOz;
    always @(posedge SBYTECLK, posedge reset)
        if(reset) begin
            tNAO <= 0; tNBOx <= 0; tNBOy <= 0; tNCOx <= 0; tNCOy <= 0;
            tNDO <= 0; tNEOx <= 0; tNEOy <= 0; tNIOw <= 0; tNIOx <= 0; tNIOy <= 0; tNIOz <= 0;
        end else begin
            tNAO <= A; tNBOx <= B & !L40; tNBOy <= L04; tNCOx <= L04 | C;
            tNCOy <= E & D & !C & !B & !A; tNDO <= D & !(A & B & C);
            tNEOx <= E | L13; tNEOy <= !(E & D & !C & !B & !A);
            tNIOw <= (L22 & !E) | (E & L40); tNIOx <= E & !D & !C & !(A & B);
            tNIOy <= K & E & D & C & !B & !A; tNIOz <= E & !D & C & !B & !A;
        end
    assign NAO = tNAO; assign NBO = tNBOx | tNBOy; assign NCO = tNCOx | tNCOy;
    assign NDO = tNDO; assign NEO = tNEOx & tNEOy; assign NIO = tNIOw | tNIOx | tNIOy | tNIOz;
 
    reg alt7, tNFO, tNGO, tNHO, tNJO;
    always @(posedge SBYTECLK, posedge reset)
        if(reset) begin alt7 <= 0; tNFO <= 0; tNGO <= 0; tNHO <= 0; tNJO <= 0; end
        else begin
            alt7 <= F & G & H & (K | (disparity ? (!E & D & L31) : (E & !D & L13)));
            tNFO <= F; tNGO <= G | (!F & !G & !H); tNHO <= H; tNJO <= !H & (G ^ F);
        end
    assign NFO = tNFO & !alt7; assign NGO = tNGO; assign NHO = tNHO; assign NJO = tNJO | alt7;
endmodule
 
// ==========================================================
// МОДУЛЬ ДЕКОДЕРА 
// ==========================================================
module decoder_8b10b (
    input reset,
    input RBYTECLK,
    input [9:0] tbi,
    output reg K_out,
    output reg [7:0] ebi,
    output reg coding_err,
    output reg disparity,
    output disparity_err
);
    wire a,b,c,d,e,i,f,g,h,j;
    assign {a,b,c,d,e,i,f,g,h,j} = tbi[9:0];
    wire AEQB, CEQD, P22, P13, P31;
    wire eeqi, KA, KB, KC, K, A, B, C, D, E, F, G, H, K28p;
    
    assign AEQB = (a & b) | (!a & !b);
    assign CEQD = (c & d) | (!c & !d);
    assign P22 = (a & b & !c & !d) | (c & d & !a & !b) | (!AEQB & !CEQD);
    assign P13 = (!AEQB & !c & !d) | (!CEQD & !a & !b);
    assign P31 = (!AEQB & c & d) | (!CEQD & a & b);
    assign eeqi = (e == i);
    assign KA = (c & d & e & i) | (!c & !d & !e & !i);
    assign KB = P13 & (!e & i & g & h & j);
    assign KC = P31 & (e & !i & !g & !h & !j);
    assign K = KA | KB | KC;
 
    assign A = a ^ ((P13 & !e) | (P22 & !a & !c & (e==i)) | (a & b & e & i) | (!c & !d & !e & !i) | (P31 & i));
    assign B = b ^ ((a & b & e & i) | (!c & !d & !e & !i) | (P31 & i) | (P31 & i) | (P22 & b & c & (e==i)) | (P22 & a & c & (e==i)) | (P13 & !e));
    assign C = c ^ ((P22 & !a & !c & (e==i)) | (P13 & !e) | (P31 & i) | (P22 & b & c & (e==i)) | (P13 & !e) | (!c & !d & !e & !i) | (!a & !b & !e & !i));
    assign D = d ^ ((a & b & e & i) | (!c & !d & !e & !i) | (P31 & i) | (P22 & a & c & (e==i)) | (P13 & !e) | (P13 & d & e & i) | (P22 & !b & !c & (e==i)));
    assign E = e ^ ((P13 & !e) | (!c & !d & !e & !i) | (!a & !b & !e & !i) | (P22 & !a & !c & (e==i)) | (P13 & !i) | (P13 & d & e & i) | (P22 & !b & !c & (e==i)));
 
    assign K28p = !(c | d | e | i);
    assign F = (j & !f & (h | !g | K28p)) | (f & !j & (!h | g | !K28p)) | (K28p & g & h) | (!K28p & !g & !h);
    assign G = (j & !f & (h | !g | !K28p)) | (f & !j & (!h | g | K28p)) | (!K28p & g & h) | (K28p & !g & !h);
    assign H = ((j ^ h) & !((!f & g & !h & j & !K28p) | (!f & g & h & !j & K28p) | (f & !g & !h & j & !K28p) | (f & !g & h & !j & K28p))) | (!f & g & h & j) | (f & !g & !h & !j);
 
    always @(posedge RBYTECLK or posedge reset)
        if (reset) begin K_out <= 0; ebi <= 8'b0; end
        else begin K_out <= K; ebi <= {H, G, F, E, D, C, B, A}; end
 
    // Диспарити 
    assign disparity_err = 0; // Для симуляції
    always @(posedge RBYTECLK or posedge reset)
        if (reset) begin coding_err <= 0; disparity <= 0; end
        else coding_err <= 0;
endmodule