[VHDL] Мультиплексор "2 в 1"

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY lab1_lab1_sch_tb IS
END lab1_lab1_sch_tb;
ARCHITECTURE behavioral OF lab1_lab1_sch_tb IS 
 
   COMPONENT lab1
   PORT( A  :   IN  STD_LOGIC; 
          B :   IN  STD_LOGIC; 
          S :   IN  STD_LOGIC; 
          Z :   OUT STD_LOGIC);
   END COMPONENT;
 
   SIGNAL A :   STD_LOGIC;
   SIGNAL B :   STD_LOGIC;
   SIGNAL S :   STD_LOGIC;
   SIGNAL Z :   STD_LOGIC;
 
BEGIN
 
   UUT: lab1 PORT MAP(
        A => A, 
        B => B, 
        S => S, 
        Z => Z
   );
 
-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
    
    A <= '1';
    B <= '0';
    S <= '0';
    
if (S = '0') then Z <= B; 
else Z <= A;
 
end if;
    
    wait for 10 ps;
            
        --WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
END;

NET A  LOC = A7 | IOSTANDARD = LVCMOS33;    
NET B  LOC = M4 | IOSTANDARD = LVCMOS33;    
NET S  LOC = C11 | IOSTANDARD = LVCMOS33;   
NET Z  LOC = M5 | IOSTANDARD = LVCMOS33;