Всё что нашёл без отладки - исправил.

module Trs
(input S, R, output Q);
xor xor_01 (G,S,Q);
DLC dlc_01 (Q,S,G,R);
endmodule
 
module Cascad
(input StartTact,  InJamp, trsCommand, TrsStep, output MemoriOut);
and an2(an2_0,  trsCommand, TrsStep);
and an3(an3_0,  InJamp, an2_0);
and an4(MemoriOut,  an3_0, StartTact);
endmodule
 
 
module MyCF
(input Deactivat,StartTact, Set, ResLim, ResFil, Fillsin, limit,  Run, Zero, Unit, InJampM, InFillsin, InStub1, InFStub, InFStub1, Sel, Sel2,  
 output  Finish, OutJamp, OutFillsin, OutStub1, OutFStub, OutFStub1,  MemoriOut);
wire TrsStep, InJamp;
 
bufif1 bf0(InFillsin, Fillsin, Sel);
Trs Fill(InFillsin, ResFil, trsFill);
and a0(f1_0, Sel, limit);
Trs TrsLim(f1_0, ResLim, OutFStub);
not n0(OutFStub1, OutFStub);
xor x0(x0_0, OutFStub1, Sel2);
//bufif1 bf1(InFillsin, InFStub1, InFStub);
bufif1 bf2(OutFillsin, InFillsin, x0_0);
 
and an0(an0_0,  trsFill, Unit);
and an1(an1_0,  trsFill, Zero);
Trs Command(an0_0, an1_0, trsCommand);
Cascad Cs_01(StartTact,  InJamp, trsCommand, TrsStep, MemoriOut);
and an5(InJamp, Sel, Run);
bufif1 bf4(Deact, MemoriOut, Deactivat);
Trs Step(Set, Deact, TrsStep);
xor x1(x1_0, trsCommand, TrsStep);
and an6(InJamp1,  x1_0, x0_0);
bufif1 bf5(OutJamp, InJamp, InJamp1);//bufif1 bf5(OutJamp, InJamp, x1_0);
not n1(OutStub11, x1_0);
bufif1 bf6(OutJamp, x1_0, OutStub11);
 
and an7(Finish,  MemoriOut, OutFStub);
 
endmodule
 
module MyC
(input Deactivat,StartTact, Set, ResLim, ResFil, Fillsin, limit,  Run, Zero, Unit, InJamp, InFillsin, InStub1, InFStub, InFStub1, Sel, Sel2,
 output  Finish, OutJamp, OutFillsin, OutStub1, OutFStub, OutFStub1,  MemoriOut, Se2);
wire sig0;
bufif1 bf0(InFillsin, Fillsin, Sel);
Trs trsFill(InFillsin, ResFil, trs0_0);
and a0(f1_0, Sel, limit);
Trs trsLim(f1_0, ResLim, OutFStub);
not n0(OutFStub1, OutFStub);
xor x0(x0_0, OutFStub1, Sel2);
bufif1 bf1(InFillsin, InFStub1, InFStub);
bufif1 bf2(OutFillsin, InFillsin, x0_0);
and an0(an0_0,  trs0_0, Unit);
and an1(an1_0,  trs0_0, Zero);
Trs Command(an0_0, an1_0, trsCommand);
//and an2(an2_0,  sig0, trs2_0);
//and an3(an3_0,  InJamp, an2_0);
//and an4(MemoriOut,  an3_0, StartTact);
Cascad Cs_01(StartTact,  InJamp, trsCommand, TrsStep, MemoriOut);
and an5(an5_0, Sel, Run);
bufif1 bf3(InJamp, an5_0, an5_0);
bufif1 bf4_(Deact, MemoriOut, Deactivat);
Trs Step(Set, Deact, TrsStep);
xor x1(x1_0, trsCommand, TrsStep);
//bufif0 bf4(InJamp, InStub1, InStub1);
and an6(InJamp1,  x1_0, x0_0);
//and an6(an6_0,  x1_0, x0_0);
//assign OutStub1 = x1_0;//not n1(OutStub1, x1_0);
bufif1 bf5(OutJamp, InJamp, InJamp1);
and an7(Finish,  MemoriOut, OutFStub);
not n1(OutStub11, x1_0);
bufif1 bf6(OutJamp, x1_0, OutStub11);
assign Se2 = Sel;
endmodule
 
module Smalch (input mset, mreset, output mquit, mquit1);
Trs Deff_01(mquit,mreset,Out1);
Trs Deff_02(Out1,mreset,Out2);
Trs Deff_03(Out2,,mquit1);
not not_01(mquit, mquit1);
endmodule
 
module Smalch1 (input mset, mreset, output mquit, rquit);
Trs Deff_01(mset,mreset,Out1);
Trs Deff_02(Out1,mreset,rquit);
Trs Deff_03(rquit,mreset,mquit);
endmodule
 
module Lancher (output limit,fillsin,unit,StartRun, One, Zero);
wire Off_01, Off_02, Off_03, Off_04;
Smalch smch1(,Off_01,limit,over);
Smalch1 smch2(over,Off_02,fillsin,Off_01);
Smalch1 smch3(fillsin, off,unit,Off_02);
Smalch1 smch4(Off_02,Off_03,Off_03,StartRun);
Trs _One_Zero(limit,, One);
not (Zero,One);
endmodule
 
module BlockSm1(input In, output out1,out2,out3);
wire w1,w2,w3,w4,w5;
Smalch1(In,w2,w1,out1);
Smalch1(w1,w3,out2,w2);
Smalch1(out2,w4,out3,w3);
Smalch1(out3,w5,w5,w4);
endmodule
 
module Key2 (input Key1,Key2,output Ok);
bufif1 (Ok,Key1,Key1);
bufif1(Ok,Key2,Key2);
endmodule
 
module Key2G1 (input Key1,Key2,Gen,output Ok1, Ok2);
bufif1 (Ok1,Key1,Gen);
bufif1(Ok2,Key2,Gen);
endmodule
 
module MyCount
(input clk, sens, output ld);
reg [25:0] count =1;
reg led_reg = 0;
assign ld = led_reg;
wire sens1;
assign sens1 = sens; 
always @ (posedge clk)
 
begin
if (sens1 == 1) begin
led_reg = 0;
 count = count +1;
if (count == 50000000) begin
count <= 1;
led_reg = 1;
end
end
end
endmodule
 
module Run (input clk, Memori,  finish, StartRun, output Deactivat, Tact, Load);
wire onPause1,Wi1,Wi2,Wi3,Wi4,Wi5;
MyCount (clk,onPause1,ld);
xor xor_01(onPause,Memori,finish);
and (onPause2,Memori,finish);
Key2 _K2in1(onPause,onPause2,onPause1);
Key2G1 _1G2in1(onPause,onPause2,ld,BeginTact,BeginLoad);
Key2 KBeginTact(BeginTact,Wi3,StartTact);
BlockSm1 Tact1(StartTact,Wi1,ResTrs,SetTRS);
Key2 _K2in2(Wi1,Wi2,Deactivat);
Key2 _K2in22(SetTRS,StartRun,SetTRS1);
Trs _Tact(SetTRS1,ResTrs,Tact);
BlockSm1 Load1(BeginLoad,Wi2,Load,Wi3);
endmodule
 
module Mych(input clk, output wire led0,led1, led2,led3,led4,led5);
wire MSypple = 0;
wire  [0:0]se[0:5];
wire  [0:0]se2[0:5];
wire  [0:0]lim[0:5];
wire  [0:0]Fills[0:5];
wire [0:0]ActivMemo[0:5];
wire Start0,Start, Start1,  Set, Fillsin1, EndFillsin, StartTact1;
wire Finish, FinishTact, Unit,InJamp, StartTact,Deactivation, One, Zero;
wire sens, led;
wire limfil,fils;
genvar i;
generate
wire [0:2]OtJam, OutFillsi[0:5], OutStu1[0:5], OutFStu[0:5], OutFStu1[0:5], ORi[0:5], Fini[0:5];
MyCF mycf(Deactivation,StartTact, Set,  ResLim, ResFil, fils, limfil, One, Zero, Unit,InJamp,,,,
,fils,se2[0],Fini[0],ORi[0], OutFillsi[0], OutStu1[0], OutFStu[0], OutFStu1[0], ActivMemo[0]);
bufif1 bf0(FinishTact, ActivMemo[0], ActivMemo[0]);
bufif1 bf1(Finish, Fini[0], Fini[0]);
for (i=0; i<4; i=i+1 ) begin:MyC_generation
MyC myc(Deactivation,StartTact, Set,  ResLim, ResFil, fils, limfil, One, Zero, Unit, ORi[i], OutFillsi[i], , OutFStu[i], OutFStu1[i]
,Zero,se2[i+1], Fini[i+1],ORi[i+1], OutFillsi[i+1], , OutFStu[i+1], OutFStu1[i+1], ActivMemo[i+1], se2[i]);//OutStu1[i]
bufif1 bf0(FinishTact, ActivMemo[i+1], ActivMemo[i+1]);
bufif1 bf1(Finish, Fini[i+1], Fini[i+1]);
end
MyC myc(Deactivation,StartTact, Set,  ResLim, ResFil, fils,  limfil, One, Zero, Unit, ORi[4], OutFillsi[4], , OutFStu[4], OutFStu1[4]
, limfil,se2[5], Fini[5],ORi[5], OutFillsi[5], , OutFStu[5], OutFStu1[5], ActivMemo[5], se2[4]);
 
endgenerate
 
Lancher Lanch_01(limfil,fils,Unit,StartRun, One, Zero);
Run(clk,FinishTact,Finish,StartRun,Deactivation,StartTact,Set);
 
not (led0 , ActivMemo [0]);
not (led1 , ActivMemo [1]);
not (led2 , ActivMemo [2]);
not (led3 , ActivMemo [3]);
not (led4 , ActivMemo [4]);
not (led5 , ActivMemo [5]);
endmodule